omarsamehsyam/Xentrix

Fine-tuned Qwen 3.5-2B for Hardware Circuit Analysis

Model Description

This repository hosts a meticulously fine-tuned version of the Qwen/Qwen3.5-2B language model, specifically engineered to understand, analyze, and summarize electronic hardware circuits. Leveraging Low-Rank Adaptation (LoRA), this model was trained on a unique, synthetically generated dataset of 1000 diverse hardware circuits, encompassing both Power Electronics and High-Speed Design domains. Each circuit in the dataset is enriched with detailed specifications, Bill of Materials (BOM), Altium netlists, and LTspice netlists.

The model's core strength lies in its ability to parse complex circuit descriptions and netlists to provide intelligent insights. It is a powerful tool for:

• Power Electronics Analysis: Interpreting circuits like Buck, Boost, Buck-Boost converters, LDOs, Flyback converters, and more. It can extract critical parameters such as input/output voltages, currents, efficiencies, and switching frequencies.
• High-Speed Design Analysis: Understanding sophisticated high-speed interfaces including USB ReDrivers, HDMI Retimers, PCIe Signal Conditioners, Ethernet PHYs, and LVDS drivers. It focuses on parameters like data rates, voltage levels, number of channels, and jitter specifications.

Key Capabilities & Use Cases

Given a comprehensive input that includes a circuit's name, category, detailed specifications, Altium netlist, and LTspice netlist, the model can generate a concise yet informative summary. This includes:

• Circuit Function Summary: A high-level overview of what the circuit does.
• Key Component Identification: Highlighting essential components from the provided Bill of Materials.
• Simulation Setup Description: Explaining the intended simulation environment and type (e.g., transient analysis, DC analysis) based on the LTspice netlist.
• Potential Applications: Suggesting suitable use cases for the analyzed circuit.

This model is ideal for hardware engineers, students, and researchers looking to quickly understand complex circuit designs, automate documentation, or derive insights from netlist data.

How to Use

To interact with this fine-tuned model, you can load it using the transformers library and provide a structured prompt. The prompt should mirror the format used during training, incorporating all available circuit details and netlists.

Example Usage (Python)

import torch
from transformers import AutoTokenizer, AutoModelForCausalLM
from peft import PeftModel

# Define the base model and fine-tuned adapter ID
base_model_name = "Qwen/Qwen3.5-2B"
lora_model_id = "omarsamehsyam/Xentrix"

# Load the tokenizer
tokenizer = AutoTokenizer.from_pretrained(base_model_name, trust_remote_code=True, padding_side="left")
if tokenizer.pad_token is None:
    tokenizer.pad_token = tokenizer.eos_token

# Load the base model in 4-bit quantization for efficiency
base_model = AutoModelForCausalLM.from_pretrained(
    base_model_name,
    trust_remote_code=True,
    torch_dtype=torch.bfloat16,
    device_map="auto",
    low_cpu_mem_usage=True
)

# Load the fine-tuned LoRA adapter onto the base model
model = PeftModel.from_pretrained(base_model, lora_model_id)
model.eval()

# Determine the device for inference
device = torch.device("cuda" if torch.cuda.is_available() else "cpu")
model.to(device)

# Construct the test prompt with example circuit data and netlists
test_prompt = (
    'Analyze this circuit with its netlists:

'
    'Name: Buck Converter
'
    'Category: Power Electronics
'
    'Description: Efficient DC-DC conversion for embedded systems.
'
    'Specifications: vin:24V, vout:17V, current:3A, efficiency:92%, fsw:500kHz

'
    'Altium Netlist:
'
    'J1,1,0,VIN
'
    'J2,2,0,GND
'
    'U1,PIN1,PIN2,LM27761
'
    'L1,SW,VOUT,10uH
'
    'C1,VOUT,GND,47uF

'
    'LTspice Netlist:
'
    '* Buck Converter Example
'
    'VIN VIN 0 DC 24
'
    'CIN VIN 0 10uF
'
    'XU1 PIN1,PIN2,PIN3,PIN4 LM27761
'
    'L1 SW VOUT 10uH
'
    'C1 VOUT 0 47uF
'
    '.tran 0 1m 0 10n
'
    '.end

'
    'Provide summary with key components and simulation setup:'
)

# Tokenize the input and move to the appropriate device
inputs = tokenizer(test_prompt, return_tensors="pt", truncation=True, max_length=1024)
inputs = {k: v.to(device) for k, v in inputs.items()}

# Generate the response
with torch.no_grad():
    outputs = model.generate(
        **inputs,
        max_new_tokens=250, # Increased token generation for more detailed summaries
        temperature=0.7, # Adjusted for more creative but still coherent output
        do_sample=True,
        top_p=0.9, # Sampling strategy
        pad_token_id=tokenizer.pad_token_id,
        eos_token_id=tokenizer.eos_token_id
    )

# Decode and print the generated response
response = tokenizer.decode(outputs[0], skip_special_tokens=True)
if "Provide summary" in response:
    response = response.split("Provide summary")[-1].strip()

print(response)

Training Details

This model was fine-tuned in a Google Colab environment using the following configurations:

• Base Model: Qwen/Qwen3.5-2B
• Fine-tuning Method: LoRA (Low-Rank Adaptation) for efficient tuning of large language models.
• Dataset: A custom, synthetically generated dataset named hardware_circuits_dataset.jsonl. It comprises 1000 entries (500 Power Electronics circuits and 500 High-Speed Design circuits), each featuring:
  • Unique ID and Name
  • Category (Power Electronics or High-Speed Design)
  • Detailed Description
  • Key Specifications (e.g., voltage, current, data rate)
  • Altium Netlist (simplified representation)
  • LTspice Netlist (for simulation)
  • Bill of Materials (BOM) with component details.
• LoRA Configuration:
  • r: 16 (LoRA attention dimension)
  • lora_alpha: 32 (Scaling factor for LoRA)
  • lora_dropout: 0.1 (Dropout probability for LoRA layers)
  • target_modules: ["q_proj", "v_proj", "k_proj", "o_proj"] (Targeted attention layers for LoRA)
• Training Parameters:
  • Epochs: 2
  • Batch Size: 1 (effective batch size 2 with gradient accumulation)
  • Gradient Accumulation Steps: 2
  • Learning Rate: 2e-4
  • Max Sequence Length: 1024 tokens (allowing for detailed netlist inclusion)
• Hardware: Trained on a single GPU (e.g., NVIDIA T4 available in Colab) with 4-bit quantization (bnb_4bit_quant_type="nf4").

Dataset & Notebook

The synthetic dataset hardware_circuits_dataset.jsonl used for training, along with this Google Colab notebook (Qwen_3.5_2B_Hardware_Circuits_Fine_Tuning.ipynb), are also available in this repository. This allows for full reproducibility and further experimentation.

License

This model and associated code are released under the Apache 2.0 License.